; various machine registers that appear in I/O space
reg_psw         == {8}177776 ; the psw
reg_cpu_error   == {8}177766 ; cpu error: various error bits
reg_pirq        == {8}177772 ; programmed interrupt request
reg_maint       == {8}177750 ; maintenance bits
reg_mmr0        == {8}177572 ; memory management register 0
reg_mmr1        == {8}177574 ; memory management register 1
reg_mmr2        == {8}177576 ; memory management register 2
reg_mmr3        == {8}177516 ; memory management register 3
reg_micro_break == {8}177770 ; microprogram breakpoint
reg_stack_limit == {8}177774 ; stack limit
reg_switch      == {8}177570 ; console switches
reg_cache_ctl   == {8}177746 ; cache control
reg_hit_miss    == {8}177752 ; hit/miss shift register
reg_mem_sys_err == {8}177744 ; memory subsystem error bits

; these are base addresses
reg_pdr_u_i == {8}177600
reg_pdr_u_d == {8}177620
reg_par_u_i == {8}177640
reg_par_u_d == {8}177660
reg_pdr_s_i == {8}172200
reg_pdr_s_d == {8}172220
reg_par_s_i == {8}172240
reg_par_s_d == {8}172260
reg_pdr_k_i == {8}172300
reg_pdr_k_d == {8}172320
reg_par_k_i == {8}172340
reg_par_k_d == {8}172360

reg_uba_map == {8}170200

; defines related to the above registers (mostly bit definitions)
; psw
reg_psw_cm  == {8}140000 ; current access mode
reg_psw_pm  == {8}030000 ; previous access mode
reg_psw_rs  == {8}004000 ; register set
reg_psw_pri == {8}000340 ; interrupt priority
reg_psw_t   == {8}000020 ; trace
reg_psw_n   == {8}000010 ; negative
reg_psw_z   == {8}000004 ; zero
reg_psw_v   == {8}000002 ; overflow
reg_psw_c   == {8}000001 ; carry
reg_psw_cc  == (reg_psw_n|reg_psw_z|reg_psw_v|reg_psw_c) ; the condition codes
; cpu error
reg_cpu_error_ill_halt == {8}000200 ; illegal halt
reg_cpu_error_addr_err == {8}000100 ; addressing error (currently, word access at an odd address)
reg_cpu_error_nxm_err  == {8}000040 ; NXM error (bus timeout)
reg_cpu_error_io_timo  == {8}000020 ; bus timeout when accessing I/O space
reg_cpu_error_y_stack  == {8}000010 ; yellow stack trap
reg_cpu_error_r_stack  == {8}000004 ; red stack trap
; pirq
; high byte is bitmask of priorities for which interrupts are requested; level n is bit 1<<(n+8)
; low byte is 0x22 times highest priority requested
; maint
reg_maint_bootaddr == {8}170000 ; user boot address (for poweropt_userboot)
reg_maint_fpaavail == {8}000400 ; FPA-available
reg_maint_moduleid == {8}000360 ; module ID:
reg_maint_moduleid_kdj11a == {8}000040 ; KDJ11-A - what do other values mean?
reg_maint_haltopt  == {8}000010 ; halt option:
reg_maint_haltopt_trap4 == {8}000010 ; ksp=4, trap to 4
reg_maint_haltopt_odt   == {8}000000 ; enter ODT
reg_maint_poweropt == {8}000006 ; power-up option:
reg_maint_poweropt_trap24   == {8}000000 ; pc from 24, psw from 26
reg_maint_poweropt_odt      == {8}000002 ; enter ODT
reg_maint_poweropt_173000   == {8}000004 ; pc = 173000, psw = 000340
reg_maint_poweropt_userboot == {8}000006 ; pc = (maint & boot_address), psw = 000340
reg_maint_dcok     == {8}000001 ; DC power OK
; mmr0
reg_mmr0_nonres  == {8}100000 ; trap was due to non-resident page
reg_mmr0_len_err == {8}040000 ; trap was due to length violation
reg_mmr0_ro_err  == {8}020000 ; trap was due to write to read-only page
reg_mmr0_accmode == {8}000140 ; access mode of trapped reference
reg_mmr0_space   == {8}000020 ; space of trap:
reg_mmr0_space_i == {8}000000 ; I space
reg_mmr0_space_d == {8}000020 ; D space
reg_mmr0_pageno  == {8}000016 ; page number of trapped reference
reg_mmr0_mm_enb  == {8}000001 ; global memory-management enable
; mmr3
reg_mmr3_uninterp == {8}000040 ; uninterpreted; can be set or cleared but has no effect
reg_mmr3_22_bit   == {8}000020 ; 22-bit mode, else 18-bit
reg_mmr3_csm_enb  == {8}000010 ; csm instruction enable
reg_mmr3_split_k  == {8}000004 ; split I/D for kernel mode
reg_mmr3_split_s  == {8}000002 ; split I/D for supervisor mode
reg_mmr3_split_u  == {8}000001 ; split I/D for user mode
; pdr (there are 16 for each access mode, 8 each I and D)
reg_pdr_nc  == {8}100000 ; no-cache: don't cache references through this mapping
reg_pdr_len == {8}077400 ; length field, used to trap out-of-bounds references
reg_pdr_w   == {8}000100 ; write, automatically set on writes through this mapping
reg_pdr_ed  == {8}000010 ; expand downwards: length check is reversed
reg_pdr_acc == {8}000006 ; access (4 is illegal, works like 0):
reg_pdr_acc_nonresident == {8}000000 ; non-resident
reg_pdr_acc_readonly    == {8}000002 ; read-only
reg_pdr_acc_readwrite   == {8}000006 ; read-write
; pirq
reg_pirq_vector == {8}240